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? freescale semiconductor, inc., 2003 , 2006. all rights reserved. freescale semiconductor technical data this document contains de tailed information on power considerations, dc/ac electrical characteristics, and ac timing specifications for .25 m (hip4) devices in the powerquicc ii? mpc8260 communications processor family. these devices include the mpc8260, the mpc8255, the mpc8264, the mpc8265, and the mpc8266. throughout this document, these devices are collectively referred to as the mpc826xa. document number: mpc8260aec rev. 1.1, 03/2006 contents 1. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2. electrical and thermal characteristics . . . . . . . . . . . . 7 3. clock configuration modes . . . . . . . . . . . . . . . . . . . 23 4. pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5. package description . . . . . . . . . . . . . . . . . . . . . . . . . 46 6. ordering information . . . . . . . . . . . . . . . . . . . . . . . . 48 7. document revision history . . . . . . . . . . . . . . . . . . . 48 mpc8260a powerquicc? ii integrated communications processor hardware specifications
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 2 freescale semiconductor features figure 1 shows the block diagram for the mpc8266, the hi p4 superset device. shaded portions indicate functionality that is not available on all devices; refer to the notes. figure 1. mpc8266 block diagram 1 features the major features of the mpc826xa family are as follows: dual-issue integer core ? a core version of the ec603e microprocessor ? system core microprocessor s upporting frequencies of 150?300 mhz ? separate 16-kbyte data and instruction caches: ? four-way set associative ? physically addressed ? lru replacement algorithm 16 kbytes g2 core i-cache i-mmu 16 kbytes d-cache d-mmu communication processor module (cpm) timers parallel i/o baud rate generators 32 kbytes 32-bit risc microcontroller and program rom serial dmas 4 virtual idmas 60x-to-pci bridge 2,3 bridge memory controller clock counter system functions system interface unit (siu) local bus 32 bits, up to 83 mhz pci bus 2,3 32 bits, up to 66 mhz or mcc1 4 mcc2 fcc1 fcc2 fcc3 4 scc1 scc2 scc3 scc4 smc1 smc2 spi i 2 c serial interface 3 mii 2 utopia ports ports 6 60x bus microcode ima 1,3 dual-port ram interrupt controller time slot assigner tc layer hardware 1,3 8 tdm ports 5 non-multiplexed i/o 60x-to-local bus interface unit notes: 1 mpc8264 2 mpc8265 3 mpc8266 4 not on mpc8255 5 4 tdm ports on the mpc8255 6 2 mii ports on the mpc8255
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 3 features ? powerpc architecture-compliant memory management unit (mmu) ? common on-chip processor (cop) test interface ? high-performance (6.6?7.65 spec95 benchmark at 300 mhz; 1.68 mips/mhz without inlining and 1.90 dhrystones mips/mhz with ? supports bus snooping for data cache coherency ? floating-point unit (fpu) separate power supply for internal logic and for i/o separate plls for g2 core and for the cpm ? g2 core and cpm can run at different frequencies for power/performance optimization ? internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios ? internal cpm/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios 64-bit data and 32-bit address 60x bus ? bus supports multiple master designs ? supports single- and four-beat burst transfers ? 64-, 32-, 16-, and 8-bit port sizes c ontrolled by on-chip memory controller ? supports data parity or ecc and address parity 32-bit data and 18-bit address local bus ? single-master bus, supports external slaves ? eight-beat burst transfers ? 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller 60x-to-pci bridge (mpc8265 and mpc8266 only) ? programmable host bridge and agent ? 32-bit data bus, 66 mhz, 3.3 v ? synchronous and asynchronous 60x and pci clock modes ? all internal address space available to external pci host ? dma for memory block transfers ? pci-to-60x address remapping system interface unit (siu) ? clock synthesizer ? reset controller ? real-time clock (rtc) register ? periodic interrupt timer ? hardware bus monitor and software watchdog timer ? ieee 1149.1 jtag test access port twelve-bank memory controller ? glueless interface to sram, page mode sdram, dram, eprom, flash and other user- definable peripherals ? byte write enables and selectable parity generation
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 4 freescale semiconductor features ? 32-bit address decodes with programmable bank size ? three user programmable machines, general-purpose chip-select machine, and page-mode pipeline sdram machine ? byte selects for 64 bus width (60x) and byte selects for 32 bus width (local) ? dedicated interface logic for sdram cpu core can be disabled and the device can be used in slave mode to an external core communications processor module (cpm) ? embedded 32-bit communications processor (cp) uses a risc architecture for flexible support for communications protocols ? interfaces to g2 core through on-chip 32-kbyte dual-port ram and dma controller ? serial dma channels for receive and transmit on all serial channels ? parallel i/o registers with open-drain and interrupt capability ? virtual dma functionality executing memory-to-memory and memory-to-i/o transfers ? three fast communications controllers supporting the following protocols (only fcc1 and fcc2 on the mpc8255): ? 10/100-mbit ethernet/ieee 802.3 cdma/cs interface through media independent interface (mii) ? atm?full-duplex sar protocols at 155 mbps, through utopia interface, aal5, aal1, aal0 protocols, tm 4.0 cbr, vbr, ubr, abr traffic types, up to 16 k external connections ? transparent ? hdlc?up to t3 rates (clear channel) ? two multichannel controllers (mccs) (only mcc2 on the mpc8255) ? each mcc handles 128 serial, full-duplex, 64-kbps data channels.each mcc can be split into four subgroups of 32 channels each. ? almost any combination of subgroups can be multiplexed to single or multiple tdm interfaces up to four tdm interfaces per mcc ? four serial communications controllers (sccs) identical to those on the mpc860, supporting the digital portions of the following protocols: ? ethernet/ieee 802.3 cdma/cs ? hdlc/sdlc and hdlc bus ? universal asynchronous receiver transmitter (uart) ? synchronous uart ? binary synchronous (bisync) communications ? transparent ? two serial management controllers (smcs), identical to those of the mpc860 ? provide management for bri devices as general circuit interface (gci) controllers in time- division-multiplexed (tdm) channels
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 5 features ? transparent ? uart (low-speed operation) ? one serial peripheral interface identical to the mpc860 spi ? one inter-integrated circuit (i 2 c) controller (identical to the mpc860 i 2 c controller) ? microwire compatible ? multiple-master, single-master, and slave modes ? up to eight tdm interfaces (four on the mpc8255) ? supports two groups of four tdm channels for a total of eight tdms ? 2,048 bytes of si ram ? bit or byte resolution ? independent transmit and receive routing, frame synchronization ? supports t1, cept, t1/e1, t3/e3, pulse code modulation highway, isdn basic rate, isdn primary rate, freescale interchip digital link (idl), general circuit interface (gci), and user-defined tdm serial interfaces ? eight independent baud rate ge nerators and 20 input clock pins for supplying clocks to fccs, sccs, smcs, and serial channels ? four independent 16-bit timers that can be interconnected as two 32-bit timers additional features of the mpc826xa family are as follows: cpm ? 32-kbyte dual-port ram ? additional mcc host commands ? eight transfer transmission convergence (tc) layers between the tdms and fcc2 to support inverse multiplexing for atm capabilities (ima) (mpc8264 and mpc8266 only) cpm multiplexing ? fcc2 can also be connected to the tc layer. tc layer (mpc8264 and mpc8266 only) ? each of the 8 tdm channels is routed in hardware to a tc layer block ? protocol-specific overhead bits may be discar ded or routed to other controllers by the si ? performing atm tc layer functions (according to itu-t i.432) ? transmit (tx) updates - cell hec generation - payload scrambling using self synchronizing scrambler (programmable by the user) - coset generation (programmable by the user) - cell rate by inserting idle/unassigned cells ? receive (rx) updates - cell delineation using bit by bit hec checking and programmable alpha and delta parameters for the delineation state machine - payload descrambling using self synchronizing scrambler (programmable by the user)
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 6 freescale semiconductor features - coset removing (programmable by the user) - filtering idle/unassigned cells (programmable by the user) - performing hec error detection and single bit error correction (programmable by user) - generating loss of cell delineation status/interrupt (loc/lcd) ? operates with fcc2 (utopia 8) ? provides serial loop back mode ? cell echo mode is provided ? supports both fcc transmit modes ? external rate mode?idle cells are generated by the fcc (microcode) to control data rate. ? internal rate mode (sub-rate)?fcc transfers onl y the data cells using the required data rate. the tc layer generates idle/unassigned cells to maintain the line bit rate. ? supports tc-layer and pmd-wire interface (according to the atm-forum af-phy-0063.000) ? cell counters for performance monitoring ? 16-bit counters count - hec error cells - hec single bit error and corrected cells - idle/unassigned cells filtered - idle/unassigned cells transmitted - transmitted atm cells - received atm cells ? maskable interrupt is sent to the host when a counter expires ? overrun (rx cell fifo) and underrun (tx cell fifo) condition produces maskable interrupt ? may be operated at e1 and ds-1 rates. in additi on, xdsl applications at bit rates up to 10 mbps are supported pci bridge (mpc8265 and mpc8266 only) ? pci specification revision 2.2 compliant and supports frequencies up to 66 mhz ? on-chip arbitration ? support for pci to 60x memory and 60x memory to pci streaming ? pci host bridge or periphera l capabilities ? includes 4 dma channels for the following transfers: ? pci-to-60x to 60x-to-pci ? 60x-to-pci to pci-to-60x ? pci-to-60x to pci-to-60x ? 60x-to-pci to 60x-to-pci ? includes all of the configuration registers (which are automatically loaded from the eprom and used to configure the mpc8265) required by the pci standard as well as message and doorbell registers ? supports the i 2 o standard
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 7 electrical and thermal characteristics ? hot-swap friendly (supports the hot swap sp ecification as defined by picmg 2.1 r1.0 august 3, 1998) ? support for 66 mhz, 3.3 v specification ? 60x-pci bus core logic which uses a buffer pool to allocate buffers for each port ? makes use of the local bus signals, so there is no need for additional pins 2 electrical and thermal characteristics this section provides ac and dc electrical specifications and thermal characteristics for the mpc826xa. 2.1 dc electrical characteristics this section describes the dc electrical characteristics for the mpc826xa. table 1 shows the maximum electrical ratings. table 1. absolute maximum ratings (1) notes: 1. absolute maximum ratings are stress ratings only; functional operation (see ta ble 2 ) at the maximums is not guaranteed. stress beyond those listed may affect device reliability or cause permanent damage. rating symbol value unit core supply voltage (2) 2. caution: vdd/vccsyn must not exceed vddh by more than 0.4 v at any time, including during power-on reset. vdd -0.3 ? 2.5 v pll supply voltage 2. vccsyn -0.3 ? 2.5 v i/o supply voltage (3) 3. caution: vddh can exceed vdd/vccsyn by 3.3 v during power on reset by no more than 100 msec. vddh should not exceed vdd/vccsyn by more than 2.5 v during normal operation. vddh -0.3 ? 4.0 v input voltage (4) 4. caution: vin must not exceed vddh by more than 2.5 v at any time, including during power-on reset. vin gnd(-0.3) ? 3.6 v junction temperature t j 120 c storage temperature range t stg (-55) ? (+150) c
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 8 freescale semiconductor electrical and thermal characteristics table 2 lists recommended operati onal voltage conditions. note: core, pll, and i/o supply voltages vddh, vccsyn, and vdd must track each other and both must vary in the same direction?in the positive direction (+5% and +0.1 vdc) or in the negative direction (-5% and -0.1 vdc). this device contains circuitry protecting against dama ge due to high static voltage or electrical fields; however, it is advised that normal precautions be take n to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circ uit. reliability of operation is enhanced if unused inputs are tied to an appropriate l ogic voltage level (either gnd or v cc ). figure 2 shows the undershoot and overshoot voltage of th e 60x and local bus memory interface of the mpc8280. note that in pci mode the i/o interface is different. figure 2. overshoot/undershoot voltage table 2. recommended operating conditions (1) notes: 1. caution: these are the recommended and tested operating conditions. proper device operating outside of these conditions is not guaranteed. rating symbol value unit core supply voltage vdd 1.7 ? 1.9 (2) 2. cpu frequency less than or equal to 200 mhz. 1.7?2.1 (3) 3. cpu frequency greater than 200 mhz but less than 233 mhz. 1.9 ?2.2 (4) 4. cpu frequency greater than or equal to 233 mhz. v pll supply voltage vccsyn 1.7 ? 1.9 2 1.7?2.1 3 1.9?2.2 4 v i/o supply voltage vddh 3.135 ? 3.465 v input voltage vin gnd (-0.3) ? 3.465 v junction temperature (maximum) t j 105 (5) 5. note that for extended temperature parts the range is (-40) t a ? 105 t j . c ambient temperature t a 0?70 5 c gnd gnd ? 0.3 v gnd ? 1.0 v not to exceed 10% gv dd of t sdram_clk gv dd + 5% 4 v v ih v il
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 9 electrical and thermal characteristics table 3 shows dc electrical characteristics. table 3. dc electrical characteristics (1) characteristic symbol min max unit input high voltage, all inputs except clkin v ih 2.0 3.465 v input low voltage v il gnd 0.8 v clkin input high voltage v ihc 2.4 3.465 v clkin input low voltage v ilc gnd 0.4 v input leakage current, v in = vddh (2) i in ?10a hi-z (off state) leakage current, v in = vddh 2 i oz ?10a signal low input current, v il = 0.8 v i l ?1a signal high input current, v ih = 2.0 v i h ?1a output high voltage, i oh = ?2 ma except xfc, utopia mode, and open drain pins in utopia mode: i oh = -8.0ma pa[0-31] pb[4-31] pc[0-31] pd[4-31] v oh 2.4 ? v in utopia mode: i ol = 8.0ma pa[0-31] pb[4-31] pc[0-31] pd[4-31] v ol ?0.5 v
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 10 freescale semiconductor electrical and thermal characteristics i ol = 7.0ma br bg abb/irq2 ts a[0-31] tt[0-4] tbst tsize[0?3] aack artry dbg dbb /irq3 d[0-63] dp(0)/rsrv /ext_br2 dp(1)/irq1 /ext_bg2 dp(2)/tlbisync /irq2 /ext_dbg2 dp(3)/irq3 /ext_br3 /ckstp_out dp(4)/irq4 /ext_bg3 /core_srest dp(5)/tben/irq5 /ext_dbg3 dp(6)/cse(0)/irq6 dp(7)/cse(1)/irq7 psdval ta tea gbl /irq1 ci/ baddr29/irq2 wt /baddr30/irq3 l2_hit /irq4 cpu_bg/ baddr31/irq5 cpu_dbg cpu_br irq0 /nmi_out irq7 /int_out /ape poreset hreset sreset rstconf qreq v ol ?0.4 v table 3. dc electrical characteristics (1) (continued) characteristic symbol min max unit
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 11 electrical and thermal characteristics i ol = 5.3ma cs [0-9] cs (10)/bctl1 cs (11)/ap(0) baddr[27?28] ale bctl0 pwe (0:7)/psddqm( 0:7)/pbs (0:7) psda10/pgpl0 psdwe/ pgpl1 poe /psdras /pgpl2 psdcas/pgpl3 pgta/pupmwait/pgpl4/ppbs psdamux/pgpl5 lwe [0?3]lsddqm [0?3]/lbs [0?3]/pci_cfg[0?3 (3) lsda10/lgpl0/pci_modckh0 3 lsdwe/lgpl1/pci_modckh1 3 loe /lsdras /lgpl2/pci_modckh2 3 lsdcas/lgpl3/pci_modckh3 3 lgta/lupmwait/lgpl4/lpbs lsdamux/lgpl5/pci_modck 3 lwr modck1/ap(1)/tc(0)/bnksel(0) modck2/ap(2)/tc(1)/bnksel(1) modck3/ap(3)/tc(2)/bnksel(2) i ol = 3.2ma l_a14/par 3 l_a15/frame 3 /smi l_a16/trdy 3 l_a17/irdy 3 /ckstp_out l_a18/stop 3 l_a19/devsel 3 l_a20/idsel 3 l_a21/perr 3 l_a22/serr 3 l_a23/req0 3 l_a24/req1 3 /hsejsw 3 l_a25/gnt0 3 l_a26/gnt1 3 /hsled 3 l_a27/gnt2 3 /hsenum 3 l_a28/rst 3 /core_sreset l_a29/inta 3 l_a30/req2 3 l_a31 lcl_d(0-31)/ad(0-31) 3 lcl_dp(0-3)/c/be (0-3) 3 pa[0?31] pb[4?31] pc[0?31] pd[4?31] tdo v ol ?0.4 v table 3. dc electrical characteristics (1) (continued) characteristic symbol min max unit
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 12 freescale semiconductor electrical and thermal characteristics 2.2 thermal characteristics table 4 describes thermal characteristics. 2.3 power considerations the average chip-junction temperature , t j , in c can be obtained from the following: t j = t a + (p d x ja ) (1) where t a = ambient temperature c ja = package thermal resistance , junction to ambient , c/w p d = p int + p i/o p int = i dd x v dd watts (chip internal power) p i/o = power dissipation on input and output pins (determined by user) for most applications p i/o < 0.3 x p int . if p i/o is neglected , an approximate relationship between p d and t j is the following: notes: 1. the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 2. the leakage current is measured for nominal vdd, vccsyn, and vdd. 3. mpc8265 and mpc8266 only. table 4. thermal characteristics for 480 tbga package characteristics symbol value unit air flow junction to ambient ja 13 (1) notes: 1. assumes a single layer board with no thermal vias c/w nc (2) 2. natural convection 10 1 1 m/s 11 (3) 3. assumes a four layer board nc 8 3 1 m/s junction to board (4) 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. jb 4 c/w ? junction to case (5) 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). jc 1.1 c/w ?
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 13 electrical and thermal characteristics p d = k/(t j + 273 c) (2) solving equations (1) and (2) for k gives: k = p d x (t a + 273 c) + ja x p d 2 (3) where k is a constant pertaining to the particular pa rt. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k , the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a . 2.3.1 layout practices each v cc pin should be provided with a low-impedance path to the board?s power supply. each ground pin should likewise be provided with a low-impedance path to ground. the power supply pins drive distinct groups of logic on chip. the v cc power supply should be bypassed to ground using at least four 0.1 f by-pass capacitors located as close as possible to the four sides of the package. the capacitor leads and associated printed circuit traces connecting to chip v cc and ground should be kept to less than half an inch per capacitor lead. a four-layer board is recommended, employing two inner layers as v cc and gnd planes. all output pins on the mpc826xa have fast rise and fall times. printed circuit (pc) trace interconnection length should be minimized in order to minimize ove rdamped conditions and reflections caused by these fast output switching times. this recommendation particularly applies to the address and data buses. maximum pc trace lengths of six inches are recommended. capacitance calculations should consider all device loads as well as parasitic capacitances due to the pc traces. attention to proper pcb layout and bypassing becomes especially critical in systems w ith higher capacitive loads because these loads create higher transient currents in the v cc and gnd circuits. pull up all unused inputs or signals that will be inputs during reset. special care should be taken to minimize the noise levels on the pll supply pins. table 5 provides preliminary, estimated power dissipation for various configurations. note that suitable thermal management is requi red for conditions above p d = 3w (when the ambient temperature is 70 c or greater) to ensure the junction temperature does not exceed the maximum specified value. also note that the i/o power should be included when determining whether to use a heat sink. table 5. estimated power dissipation for various configurations (1) bus (mhz) cpm multiplier core cpu multiplier cpm (mhz) cpu (mhz) p int (w) (2) vddl 1.8 volts vddl 2.0 volts nominal maximum nominal maximum 66.66 2 3 133 200 1.2 2 1.8 2.3 66.66 2.5 3 166 200 1.3 2.1 1.9 2.3 66.66 3 4 200 266 ? ? 2.3 2.9 66.66 3 4.5 200 300 ? ? 2.4 3.1 83.33 2 3 166 250 ? ? 2.2 2.8 83.33 2 3 166 250 ? ? 2.2 2.8 83.33 2.5 3.5 208 291 ? ? 2.4 3.1
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 14 freescale semiconductor electrical and thermal characteristics 2.4 ac electrical characteristics the following sections include illustrations and tables of clock diagrams, signals, and cpm outputs and inputs for the 66 mhz mpc826xa device. note that ac timings are based on a 50-p f load. typical output buffer impedances are shown in table 6 . table 7 lists cpm output characteristics. notes: 1. test temperature = room temperature (25 c) 2. p int = i dd x v dd watts table 6. output buffer impedances (1) notes: 1. these are typical values at 65 c. the impedance may vary by 25% with process and temperature. output buffers typical impedance ( ? ) 60x bus 40 local bus 40 memory controller 40 parallel i/o 46 pci 25 table 7. ac characteristics for cpm outputs (1) notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic max delay (ns) min delay (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp36a sp37a fcc outputs?internal clock (nmsi) 6 5.5 1 1 sp36b sp37b fcc outputs?external clock (nmsi) 14 12 2 1 sp40 sp41 tdm outputs/si 25 16 5 4 sp38a sp39a scc/smc/spi/i2c outputs?internal clock (nmsi) 19 16 1 0.5 sp38b sp39b ex_scc/smc/spi/i2c outputs?external clock (nmsi) 19 16 2 1 sp42 sp43 timer/idma outputs 14 11 1 0.5 sp42a sp43a pio outputs 14 11 0.5 0.5
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 15 electrical and thermal characteristics table 8 lists cpm input characteristics. note that although the specifications generally refere nce the rising edge of the clock, the following ac timing diagrams also apply when the falling edge is the active edge. figure 3 shows the fcc external clock. figure 3. fcc external clock diagram table 8. ac characteristics for cpm inputs (1) notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec number characteristic setup (ns) hold (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp16a sp17a fcc inputs?internal clock (nmsi) 10 8 0 0 sp16b sp17b fcc inputs?external clock (nmsi) 3 2.5 3 2 sp20 sp21 tdm inputs/si 15 12 12 10 sp18a sp19a scc/smc/spi/i2c inputs?internal clock (nmsi) 20 16 0 0 sp18b sp19b scc/smc/spi/i2c inputs?external clock (nmsi) 5 4 5 4 sp22 sp23 pio/timer/idma inputs 10 8 3 3 serial clkin fcc input signals fcc output signals fcc output signals note : when gfmr[tci] = 1 note : when gfmr[tci] = 0 sp16b sp17b sp36b/sp37b sp36b/sp37b
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 16 freescale semiconductor electrical and thermal characteristics figure 4 shows the fcc internal clock. figure 4. fcc internal clock diagram figure 5 shows the scc/smc/spi/i 2 c external clock. figure 5. scc/smc/spi/i 2 c external clock diagram brg_out fcc input signals fcc output signals fcc output signals note : when gfmr[tci] = 1 note : when gfmr[tci] = 0 sp36a/sp37a sp36a/sp37a sp17a sp16a serial clkin scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18b sp19b sp38b/sp39b (see note.) (see note.) note : there are four possible timing conditions for scc and spi: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge.
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 17 electrical and thermal characteristics figure 6 shows the scc/smc/spi/i 2 c internal clock. figure 6. scc/smc/spi/i 2 c internal clock diagram figure 7 shows tdm input and output signals. figure 7. tdm signal diagram brg_out scc/smc/spi/i2c input signals scc/smc/spi/i2c output signals sp18a sp19a sp38a/sp39a (see note.) (see note.) note : there are four possible timing conditions for scc and spi: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge. serial clkin tdm input signals tdm output signals sp20 sp21 sp40/sp41 note : there are four possible tdm timing conditions: 1. input sampled on the rising edge and output driven on the rising edge (shown). 2. input sampled on the rising edge and output driven on the falling edge. 3. input sampled on the falling edge and output driven on the falling edge. 4. input sampled on the falling edge and output driven on the rising edge.
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 18 freescale semiconductor electrical and thermal characteristics figure 8 shows pio, timer, and dma signals. figure 8. pio, timer, and dma signal diagram table 10 lists siu input characteristics. table 9. ac characteristics for siu inputs (1) notes: 1. input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of clkin. timings are measured at the pin. spec number characteristic setup (ns) hold (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp11 sp10 aack /artry /ta /ts /tea /dbg /bg /br 650.50.5 sp12 sp10 data bus in normal mode 5 4 0.5 0.5 sp13 sp10 data bus in ecc and parity modes 8 6 0.5 0.5 sp14 sp10 dp pins 7 6 0.5 0.5 sp15 sp10 all other pins 5 4 0.5 0.5 sys clk pio/idma/timer[tgate assertion] input signals idma output signals sp22 sp23 sp42/sp43 timer(sp42/43)/ pio(sp42a/sp43a) sp42a/sp43a output signals sp42/sp43 timer input signal [tgate deassertion] sp22 sp23 note : tgate is asserted on the rising edge of the clock; it is deasserted on the falling edge. (see note) (see note)
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 19 electrical and thermal characteristics table 10 lists siu output characteristics. note activating data pi pelining (setting br x [dr] in the memory controller) improves the ac timing. when data pipelining is activated, sp12 can be used for data bus setup even when ecc or parity are used. also, sp33a can be used as the ac specification for dp signals. table 10. ac characteristics for siu outputs (1) notes: 1. output specifications are measured from the 50% level of the rising edge of clkin to the 50% level of the signal. timings are measured at the pin. spec number characteristic max delay (ns) min delay (ns) max min 66 mhz 83 mhz 66 mhz 83 mhz sp31 sp30 psdval /tea /ta 760.50.5 sp32 sp30 add/add_atr./baddr/ci/gbl/wt 8 6.5 0.5 0.5 sp33a sp30 data bus 6.5 6.5 0.5 0.5 sp33b sp30 dp 8 7 0.5 0.5 sp34 sp30 memory controller signals/ale 6 5 0.5 0.5 sp35 sp30 all other signals 6 5.5 0.5 0.5
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 20 freescale semiconductor electrical and thermal characteristics figure 9 shows the interaction of several bus signals. figure 9. bus signals figure 10 shows signal behavior for all parity modes (including ecc, rm w parity, and standard parity). figure 10. parity mode diagram clkin aack /artry /ta /ts /tea / data bus normal mode all other input signals psdval /tea /ta output signals add/add_atr/baddr/ci/ data bus output signals all other output signals sp11 sp12 sp15 sp10 sp10 sp10 sp30 sp30 sp30 sp30 sp32 sp33a sp35 dbg /bg /br input signals gbl/wt output signals sp31 input signal clkin data bus, ecc, and parity mode input signals dp mode input signal dp mode output signal sp13 sp10 sp14 sp10 sp33b/sp30
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 21 electrical and thermal characteristics figure 11 shows signal behavior in memc mode. figure 11. memc mode diagram note generally, all mpc826xa bus and system output signals are driven from the rising edge of the input clock (clkin). memory controller signals, however, trigger on four points within a clkin cycle. each cycle is divided by four internal ticks: t1, t2, t3, and t4. t1 always occurs at the rising edge, and t3 at the falling edge, of clkin. however, the spacing of t2 and t4 depends on the pll clock ratio selected, as shown in table 11 . figure 12 is a graphical representation of table 11 . figure 12. internal tick spacing for memory controller signals table 11. tick spacing for memory controller signals pll clock ratio tick spacing (t1 occurs at the rising edge of clkin) t2 t3 t4 1:2, 1:3, 1:4, 1:5, 1:6 1/4 clkin 1/2 clkin 3/4 clkin 1:2.5 3/10 clkin 1/2 clkin 8/10 clkin 1:3.5 4/14 clkin 1/2 clkin 11/14 clkin clkin v_clk memory controller signals sp34/sp30 clkin t1 t2 t3 t4 clkin t1 t2 t3 t4 for 1:2.5 for 1:3.5 clkin t1 t2 t3 t4 for 1:2, 1:3, 1:4, 1:5, 1:6
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 22 freescale semiconductor electrical and thermal characteristics table 12 lists the jtag timings. note the upm machine outputs change on the internal tick determined by the memory controller programming; the ac specifications are relative to the internal tick. note that sdram and gpcm machine outputs change on clkin?s rising edge. table 12. jtag timings 1 parameter symbol 2 min max unit notes jtag external clock frequency of operation f jtg 025mhz jtag external clock cycle time t jtg 40 ? ns jtag external clock pulse width measured at 1.4v t jtkhkl 20 ? ns jtag external clock rise and fall times t jtgr and t jtgf 05ns 6 trst assert time t trst 25 ? ns 3 , 6 input setup times boundary-scan data tms, tdi t jtdvkh t jtivkh 4 4 ? ? ns ns 4 , 7 4 , 7 input hold times boundary-scan data tms, tdi t jtdxkh t jtixkh 10 10 ? ? ns ns 4 , 7 4 , 7 output valid times boundary-scan data tdo t jtkldv t jtklov ? ? 25 25 ns ns 5 , 7 5 . 7 output hold times boundary-scan data tdo t jtkldx t jtklox 1 1 ? ? ns ns 5 , 7 5 , 7 jtag external clock to output high impedance boundary-scan data tdo t jtkldz t jtkloz 1 1 25 25 ns ns 5 , 6 5 , 6 1 all outputs are measured from the midpoint voltage of the falling/rising edge of t tclk to the midpoint of the signal in question. the output timings are measured at the pins. all output timings assume a purely resistive 50- ? load. time-of-flight delays must be added for trace lengths, vias, and connectors in the system. 2 the symbols used for timing specifications herein follow the pattern of t (first two letters of functional block)(signal)(state) (reference)(state) for inputs and t( (first two letters of functional block)(reference)(state)(signal)(state) for outputs. for example, t jtdvkh symbolizes jtag device timing (jt) with respect to the time data input signals (d) reaching the valid state (v) relative to the t jtg clock reference (k) going to the high (h) state or setup time. also, t jtdxkh symbolizes jtag timing (jt) with respect to the time data input signals (d) went invalid (x) relative to the t jtg clock reference (k) going to the high (h) state. note that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular functional. for rise and fall times, the latter convention is used with the appropriate letter: r (rise) or f (fall). 3 trst is an asynchronous level sensitive signal. the setup time is for test purposes only. 4 non-jtag signal input timing with respect to t tclk . 5 non-jtag signal output timing with respect to t tclk . 6 guaranteed by design. 7 guaranteed by design and device characterization.
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 23 clock configuration modes 3 clock configuration modes to configure the main pll multiplication factor and the core, cpm, and 60x bus frequencies, the modck[1?3] pins are sampled while hreset is asserted. table 13 lists the eight basic configuration modes. table 14 lists the other modes that are available by using the configuration pin (rstconf ) and driving four bits from hardware configuration word on the data bus. note that the mpc8265 and the mpc8266 have two a dditional clocking modes?pci agent and pci host. refer to section 3.2, ?pci mode? on page 26 for information. note clock configurations change only after por is asserted. 3.1 local bus mode table 13 describes default clock modes for the mpc826xa. table 14 describes all possible clock configurations when using the hard reset configuration sequence. note that basic modes are shown in boldface type. the frequencies listed are for the purpose of illustration only. users must select a mode and input bus frequenc y so that the resulting configuration does not exceed the frequency rating of the user?s device. table 13. clock default modes modck[1?3] input clock frequency cpm multiplication factor cpm frequency core multiplication factor core frequency 000 33 mhz 3 100 mhz 4 133 mhz 001 33 mhz 3 100 mhz 5 166 mhz 010 33 mhz 4 133 mhz 4 133 mhz 011 33 mhz 4 133 mhz 5 166 mhz 100 66 mhz 2 133 mhz 2.5 166 mhz 101 66 mhz 2 133 mhz 3 200 mhz 110 66 mhz 2.5 166 mhz 2.5 166 mhz 111 66 mhz 2.5 166 mhz 3 200 mhz table 14. clock configuration modes (1) modck_h?modck[1?3] input clock frequency (2) ,(3) cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2 0001_000 33 mhz 2 66 mhz 4 133 mhz 0001_001 33 mhz 2 66 mhz 5 166 mhz 0001_010 33 mhz 2 66 mhz 6 200 mhz 0001_011 33 mhz 2 66 mhz 7 233 mhz 0001_100 33 mhz 2 66 mhz 8 266 mhz
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 24 freescale semiconductor clock configuration modes 0001_101 33 mhz 3 100 mhz 4 133 mhz 0001_110 33 mhz 3 100 mhz 5 166 mhz 0001_111 33 mhz 3 100 mhz 6 200 mhz 0010_000 33 mhz 3 100 mhz 7 233 mhz 0010_001 33 mhz 3 100 mhz 8 266 mhz 0010_010 33 mhz 4 133 mhz 4 133 mhz 0010_011 33 mhz 4 133 mhz 5 166 mhz 0010_100 33 mhz 4 133 mhz 6 200 mhz 0010_101 33 mhz 4 133 mhz 7 233 mhz 0010_110 33 mhz 4 133 mhz 8 266 mhz 0010_111 33 mhz 5 166 mhz 4 133 mhz 0011_000 33 mhz 5 166 mhz 5 166 mhz 0011_001 33 mhz 5 166 mhz 6 200 mhz 0011_010 33 mhz 5 166 mhz 7 233 mhz 0011_011 33 mhz 5 166 mhz 8 266 mhz 0011_100 33 mhz 6 200 mhz 4 133 mhz 0011_101 33 mhz 6 200 mhz 5 166 mhz 0011_110 33 mhz 6 200 mhz 6 200 mhz 0011_111 33 mhz 6 200 mhz 7 233 mhz 0100_000 33 mhz 6 200 mhz 8 266 mhz 0100_001 reserved 0100_010 0100_011 0100_100 0100_101 0100_110 table 14. clock configuration modes (1) (continued) modck_h?modck[1?3] input clock frequency (2) ,(3) cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 25 clock configuration modes 0100_111 reserved 0101_000 0101_001 0101_010 0101_011 0101_100 0101_101 66 mhz 2 133 mhz 2 133 mhz 0101_110 66 mhz 2 133 mhz 2.5 166 mhz 0101_111 66 mhz 2 133 mhz 3 200 mhz 0110_000 66 mhz 2 133 mhz 3.5 233 mhz 0110_001 66 mhz 2 133 mhz 4 266 mhz 0110_010 66 mhz 2 133 mhz 4.5 300 mhz 0110_011 66 mhz 2.5 166 mhz 2 133 mhz 0110_100 66 mhz 2.5 166 mhz 2.5 166 mhz 0110_101 66 mhz 2.5 166 mhz 3 200 mhz 0110_110 66 mhz 2.5 166 mhz 3.5 233 mhz 0110_111 66 mhz 2.5 166 mhz 4 266 mhz 0111_000 66 mhz 2.5 166 mhz 4.5 300 mhz 0111_001 66 mhz 3 200 mhz 2 133 mhz 0111_010 66 mhz 3 200 mhz 2.5 166 mhz 0111_011 66 mhz 3 200 mhz 3 200 mhz 0111_100 66 mhz 3 200 mhz 3.5 233 mhz 0111_101 66 mhz 3 200 mhz 4 266 mhz 0111_110 66 mhz 3 200 mhz 4.5 300 mhz 0111_111 66 mhz 3.5 233 mhz 2 133 mhz 1000_000 66 mhz 3.5 233 mhz 2.5 166 mhz table 14. clock configuration modes (1) (continued) modck_h?modck[1?3] input clock frequency (2) ,(3) cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 26 freescale semiconductor clock configuration modes 3.2 pci mode the mpc8265 and the mpc8266 have three clocking mode s: local, pci host, and pci agent. the clocking mode is set according to three input pins?pci_mode, pci_cfg[0], pci_modck?as shown in table 15 . in addition, note the following: note: pci_modck in pci mode only, pci_modck comes from the lgpl5 pin and modck_h[0?3] comes from {lgpl0, lgpl1, lgpl2, lgpl3}. note: tval (output hold) the minimum tval = 2 when pci_modck = 1, and the minimum tval = 1 when pci_modck = 0. therefore, designers should use clock configurations that fit this condition to achieve pci-compliant ac timing. note clock configurations change only after por is asserted. 1000_001 66 mhz 3.5 233 mhz 3 200 mhz 1000_010 66 mhz 3.5 233 mhz 3.5 233 mhz 1000_011 66 mhz 3.5 233 mhz 4 266 mhz 1000_100 66 mhz 3.5 233 mhz 4.5 300 mhz notes: 1. because of speed dependencies, not all of the possible configurations in ta ble 1 4 are applicable. 2. the user should choose the input clock frequency and the multiplication factors such that the frequency of the cpu is equal to or greater than150 mhz and the cpm ranges between 66?233 mhz. 3. input clock frequency is given only for the purpose of reference. user should set modck_h?modck_l so that the resulting configuration does not exceed the frequency rating of the user?s part. table 15. mpc8265 and mpc8266 clocking modes pins clocking mode pci clock frequency range (mhz) pci_mode pci_cfg[0] pci_modck 1 ? ? local bus ? 0 0 0 pci host 50?66 0 0 1 25?50 0 1 0 pci agent 50?66 0 1 1 25?50 table 14. clock configuration modes (1) (continued) modck_h?modck[1?3] input clock frequency (2) ,(3) cpm multiplication factor 2 cpm frequency 2 core multiplication factor 2 core frequency 2
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 27 clock configuration modes 3.2.1 pci host mode the frequencies listed in table 16 and table 17 are for the purpose of illustration only. users must select a mode and input bus frequency so that the resu lting configuration does not exceed the frequency rating of the user?s device. i table 17 describes all possible clock configurations when using the mpc8265 or the mpc8266?s internal pci bridge in host mode. table 16. clock default configurations in pci host mode (modck_hi = 0000) modck[1?3] (1) notes: 1. assumes modck_hi = 0000. input clock frequency (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor (2) 2. the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) refer to ta b l e 1 5 . pci frequency 2 000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 001 66 mhz 2 133 mhz 3 200 mhz 2/4 66/33 mhz 010 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 011 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 100 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 101 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz 110 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 111 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz table 17. clock configuration modes in pci host mode modck_h ? modck[1?3] input clock frequency (1) (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor (2) pci frequency 2 0001_000 33 mhz 3 100 mhz 5 166 mhz 3/6 33/16 mhz 0001_001 33 mhz 3 100 mhz 6 200 mhz 3/6 33/16 mhz 0001_010 33 mhz 3 100 mhz 7 233 mhz 3/6 33/16 mhz 0001_011 33 mhz 3 100 mhz 8 266 mhz 3/6 33/16 mhz 0010_000 33 mhz 4 133 mhz 5 166 mhz 4/8 33 /16 mhz 0010_001 33 mhz 4 133 mhz 6 200 mhz 4/8 33/16 mhz 0010_010 33 mhz 4 133 mhz 7 233 mhz 4/8 33/16 mhz 0010_011 33 mhz 4 133 mhz 8 266 mhz 4/8 33/16 mhz 0011_000 (3) 33 mhz 5 166 mhz 5 166 mhz 5 33 mhz 0011_001 3 33 mhz 5 166 mhz 6 200 mhz 5 33 mhz
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 28 freescale semiconductor clock configuration modes 0011_010 3 33 mhz 5 166 mhz 7 233 mhz 5 33 mhz 0011_011 3 33 mhz 5 166 mhz 8 266 mhz 5 33 mhz 0100_000 3 33 mhz 6 200 mhz 5 166 mhz 6 33 mhz 0100_001 3 33 mhz 6 200 mhz 6 200 mhz 6 33 mhz 0100_010 3 33 mhz 6 200 mhz 7 233 mhz 6 33 mhz 0100_011 3 33 mhz 6 200 mhz 8 266 mhz 6 33 mhz 0101_000 66 mhz 2 133 mhz 2.5 166 mhz 2/4 66/33 mhz 0101_001 66 mhz 2 133 mhz 3 200 mhz 2 /4 66 /33 mhz 0101_010 66 mhz 2 133 mhz 3.5 233 mhz 2/4 66/33 mhz 0101_011 66 mhz 2 133 mhz 4 266 mhz 2/4 66/33 mhz 0101_100 66 mhz 2 133 mhz 4.5 300 mhz 2/4 66/33 mhz 0110_000 66 mhz 2.5 166 mhz 2.5 166 mhz 3/6 55/28 mhz 0110_001 66 mhz 2.5 166 mhz 3 200 mhz 3/6 55/28 mhz 0110_010 66 mhz 2.5 166 mhz 3.5 233 mhz 3/6 55/28 mhz 0110_011 66 mhz 2.5 166 mhz 4 266 mhz 3/6 55/28 mhz 0110_100 66 mhz 2.5 166 mhz 4.5 300 mhz 3/6 55/28 mhz 0111_000 66 mhz 3 200 mhz 2.5 166 mhz 3/6 66/33 mhz 0111_001 66 mhz 3 200 mhz 3 200 mhz 3/6 66/33 mhz 0111_010 66 mhz 3 200 mhz 3.5 233 mhz 3/6 66/33 mhz 0111_011 66 mhz 3 200 mhz 4 266 mhz 3/6 66/33 mhz 0111_100 66 mhz 3 200 mhz 4.5 300 mhz 3/6 66/33 mhz 1000_000 66 mhz 3 200 mhz 2.5 166 mhz 4/8 50/25 mhz 1000_001 66 mhz 3 200 mhz 3 200 mhz 4/8 50/25 mhz 1000_010 66 mhz 3 200 mhz 3.5 233 mhz 4/8 50/25 mhz 1000_011 66 mhz 3 200 mhz 4 266 mhz 4/8 50/25 mhz 1000_100 66 mhz 3 200 mhz 4.5 300 mhz 4/8 50/25 mhz 1001_000 66 mhz 3.5 233 mhz 2.5 166 mhz 4/8 58/29 mhz table 17. clock configuration modes in pci host mode (continued) modck_h ? modck[1?3] input clock frequency (1) (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor (2) pci frequency 2
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 29 clock configuration modes 3.2.2 pci agent mode the frequencies listed in table 18 and table 19 are for the purpose of illustration only. users must select a mode and input bus frequency so that the resu lting configuration does not exceed the frequency rating of the user?s device. 1001_001 66 mhz 3.5 233 mhz 3 200 mhz 4/8 58/29 mhz 1001_010 66 mhz 3.5 233 mhz 3.5 233 mhz 4/8 58/29 mhz 1001_011 66 mhz 3.5 233 mhz 4 266 mhz 4/8 58/29 mhz 1001_100 66 mhz 3.5 233 mhz 4.5 300 mhz 4/8 58/29 mhz 1010_000 100 mhz 2 200 mhz 2 200 mhz 3/6 66/33 mhz 1010_001 100 mhz 2 200 mhz 2.5 250 mhz 3/6 66/33 mhz 1010_010 100 mhz 2 200 mhz 3 300 mhz 3/6 66/33 mhz 1010_011 100 mhz 2 200 mhz 3.5 350 mhz 3/6 66/33 mhz 1010_100 100 mhz 2 200 mhz 4 400 mhz 3/6 66/33 mhz 1011_000 100 mhz 2.5 250 mhz 2 200 mhz 4/8 62/31 mhz 1011_001 100 mhz 2.5 250 mhz 2.5 250 mhz 4/8 62/31mhz 1011_010 100 mhz 2.5 250 mhz 3 300 mhz 4/8 62/31 mhz 1011_011 100 mhz 2.5 250 mhz 3.5 350 mhz 4/8 62/31 mhz 1011_100 100 mhz 2.5 250 mhz 4 400 mhz 4/8 62/31 mhz notes: 1. input clock frequency is given only for the purpose of reference. user should set modck_h?modck_l so that the resulting configuration does not exceed the frequency rating of the user?s part. 2. the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.). refer to ta b l e 1 5 . 3. in this mode, pci_modck must be ?0?. table 18. clock default configurations in pci agent mode (modck_hi = 0000) modck[1?3] (1) input clock frequency (pci) 2 cpm multiplication factor (2) cpm frequency core multiplication factor core frequency (3) bus division factor 60x bus frequency (4) 000 66/33 mhz 2/4 133 mhz 2.5 166 mhz 2 66 mhz 001 66/33 mhz 2/4 133 mhz 3 200 mhz 2 66 mhz 010 66/33 mhz 3/6 200 mhz 3 200 mhz 3 66 mhz 011 66/33 mhz 3/6 200 mhz 4 266 mhz 3 66 mhz table 17. clock configuration modes in pci host mode (continued) modck_h ? modck[1?3] input clock frequency (1) (bus) cpm multiplication factor cpm frequency core multiplication factor core frequency pci division factor (2) pci frequency 2
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 30 freescale semiconductor clock configuration modes table 19 describes all possible clock configurations when using the mpc8265 or the mpc8266?s internal pci bridge in agent mode. 100 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 101 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 110 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 111 66/33 mhz 4/8 266 mhz 3 300 mhz 2.5 100 mhz notes: 1. assumes modck_hi = 0000. 2. the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2. refer to ta ble 1 5 . 3. core frequency = (60x bus frequency)(core multiplication factor) 4. bus frequency = cpm frequency / bus division factor table 19. clock configuration modes in pci agent mode modck_h ? modck[1?3] input clock frequency (pci) (1),(2) cpm multiplication factor 1 cpm frequency core multiplication factor core frequency (3) bus division factor 60x bus frequency (4) 0001_001 66/33 mhz 2/4 133 mhz 5 166 mhz 4 33 mhz 0001_010 66/33 mhz 2/4 133 mhz 6 200 mhz 4 33 mhz 0001_011 66/33 mhz 2/4 133 mhz 7 233 mhz 4 33 mhz 0001_100 66/33 mhz 2/4 133 mhz 8 266 mhz 4 33 mhz 0010_001 50/25 mhz 3/6 150 mhz 3 180 mhz 2.5 60 mhz 0010_010 50/25 mhz 3/6 150 mhz 3.5 210 mhz 2.5 60 mhz 0010_011 50/25 mhz 3/6 150 mhz 4 240 mhz 2.5 60 mhz 0010_100 50/25 mhz 3/6 150 mhz 4.5 270 mhz 2.5 60 mhz 0011_000 66/33 mhz 2/4 133 mhz 2.5 110mhz 3 44 mhz 0011_001 66/33 mhz 2/4 133 mhz 3 132 mhz 3 44 mhz 0011_010 66/33 mhz 2/4 133 mhz 3.5 154 mhz 3 44 mhz 0011_011 66/33 mhz 2/4 133 mhz 4 176mhz 3 44 mhz 0011_100 66/33 mhz 2/4 133 mhz 4.5 198 mhz 3 44 mhz 0100_000 66/33 mhz 3/6 200 mhz 2.5 166 mhz 3 66 mhz 0100_001 66/33 mhz 3/6 200 mhz 3 200 mhz 366 mhz 0100_010 66/33 mhz 3/6 200 mhz 3.5 233 mhz 366 mhz table 18. clock default configurations in pci agent mode (modck_hi = 0000) (continued) modck[1?3] (1) input clock frequency (pci) 2 cpm multiplication factor (2) cpm frequency core multiplication factor core frequency (3) bus division factor 60x bus frequency (4)
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 31 clock configuration modes 0100_011 66/33 mhz 3/6 200 mhz 4 266 mhz 366 mhz 0100_100 66/33 mhz 3/6 200 mhz 4.5 300 mhz 366 mhz 0101_000 (5) 33 mhz 5 166 mhz 2.5 166 mhz 2.5 66 mhz 0101_001 5 33 mhz 5 166 mhz 3 200 mhz 2.5 66 mhz 0101_010 5 33 mhz 5 166 mhz 3.5 233 mhz 2.5 66 mhz 0101_011 5 33 mhz 5 166 mhz 4 266 mhz 2.5 66 mhz 0101_100 5 33 mhz 5 166 mhz 4.5 300 mhz 2.5 66 mhz 0110_000 50/25 mhz 4/8 200 mhz 2.5 166 mhz 3 66 mhz 0110_001 50/25 mhz 4/8 200 mhz 3 200 mhz 3 66 mhz 0110_010 50/25 mhz 4/8 200 mhz 3.5 233 mhz 3 66 mhz 0110_011 50/25 mhz 4/8 200 mhz 4 266 mhz 3 66 mhz 0110_100 50/25 mhz 4/8 200 mhz 4.5 300 mhz 3 66 mhz 0111_000 66/33 mhz 3/6 200 mhz 2 200 mhz 2 100 mhz 0111_001 66/33 mhz 3/6 200 mhz 2.5 250 mhz 2 100 mhz 0111_010 66/33 mhz 3/6 200 mhz 3 300 mhz 2 100 mhz 0111_011 66/33 mhz 3/6 200 mhz 3.5 350 mhz 2 100 mhz 1000_000 66/33 mhz 3/6 200 mhz 2 160 mhz 2.5 80 mhz 1000_001 66/33 mhz 3/6 200 mhz 2.5 200 mhz 2.5 80 mhz 1000_010 66/33 mhz 3/6 200 mhz 3 240 mhz 2.5 80 mhz 1000_011 66/33 mhz 3/6 200 mhz 3.5 280 mhz 2.5 80 mhz 1000_100 66/33 mhz 3/6 200 mhz 4 320 mhz 2.5 80 mhz 1000_101 66/33 mhz 3/6 200 mhz 4.5 360 mhz 2.5 80 mhz 1001_000 66/33 mhz 4/8 266 mhz 2.5 166 mhz 4 66 mhz 1001_001 66/33 mhz 4/8 266 mhz 3 200 mhz 4 66 mhz 1001_010 66/33 mhz 4/8 266 mhz 3.5 233 mhz 4 66 mhz 1001_011 66/33 mhz 4/8 266 mhz 4 266 mhz 4 66 mhz 1001_100 66/33 mhz 4/8 266 mhz 4.5 300 mhz 4 66 mhz table 19. clock configuration modes in pci agent mode (continued) modck_h ? modck[1?3] input clock frequency (pci) (1),(2) cpm multiplication factor 1 cpm frequency core multiplication factor core frequency (3) bus division factor 60x bus frequency (4)
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 32 freescale semiconductor clock configuration modes 1010_000 66/33 mhz 4/8 266 mhz 2.5 222 mhz 3 88 mhz 1010_001 66/33 mhz 4/8 266 mhz 3 266 mhz 3 88 mhz 1010_010 66/33 mhz 4/8 266 mhz 3.5 300 mhz 3 88 mhz 1010_011 66/33 mhz 4/8 266 mhz 4 350 mhz 3 88 mhz 1010_100 66/33 mhz 4/8 266 mhz 4.5 400 mhz 3 88 mhz 1011_000 66/33 mhz 4/8 266 mhz 2 212mhz 2.5 106 mhz 1011_001 66/33 mhz 4/8 266 mhz 2.5 265 mhz 2.5 106 mhz 1011_010 66/33 mhz 4/8 266 mhz 3 318 mhz 2.5 106 mhz 1011_011 66/33 mhz 4/8 266 mhz 3.5 371 mhz 2.5 106 mhz 1011_100 66/33 mhz 4/8 266 mhz 4 424 mhz 2.5 106 mhz notes: 1. the frequency depends on the value of pci_modck. if pci_modck is high (logic ?1?), the pci frequency is divided by 2 (33 instead of 66 mhz, etc.) and the cpm multiplication factor is multiplied by 2. refer to ta ble 1 5 . 2. input clock frequency is given only for the purpose of reference. user should set modck_h?modck_l so that the resulting configuration does not exceed the frequency rating of the user?s part. 3. core frequency = (60x bus frequency)(core multiplication factor) 4. bus frequency = cpm frequency / bus division factor 5. in this mode, pci_modck must be ?1?. table 19. clock configuration modes in pci agent mode (continued) modck_h ? modck[1?3] input clock frequency (pci) (1),(2) cpm multiplication factor 1 cpm frequency core multiplication factor core frequency (3) bus division factor 60x bus frequency (4)
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 33 pinout 4 pinout this section provides the pin assignments and pinout list for the mpc826xa. 4.1 pin assignments figure 13 shows the pinout of the mpc826xa?s 480 tbga package as viewed from the top surface. figure 13. pinout of the 480 tbga package as viewed from the top surface 1 2 3 4 5 6 7 8 910111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 not to scale 1 2 3 4 5 6 7 8 91011121314151617181920212223242526272829 a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj a b c d e f g h j k l m n p r t u v w y aa ab ac ad ae af ag ah aj
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 34 freescale semiconductor pinout figure 14 shows the side profile of the tbga package to indicate the direction of the top surface view. figure 14. side view of the tbga package table 20 shows the pinout list of the mpc826xa. table 21 defines conventions and acronyms used in table 20 . table 20. pinout list pin name ball br w5 bg f4 abb/irq2 e2 ts e3 a0 g1 a1 h5 a2 h2 a3 h1 a4 j5 a5 j4 a6 j3 a7 j2 a8 j1 a9 k4 a10 k3 a11 k2 a12 k1 a13 l5 a14 l4 a15 l3 a16 l2 a17 l1 soldermask copper traces die copper heat spreader (oxidized for insulation) 1.27 mm pitch glob-top dam wir e b o n ds etched pressure sensitive die glob-top filled area polymide tape cavity adhesive attach view
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 35 pinout a18 m5 a19 n5 a20 n4 a21 n3 a22 n2 a23 n1 a24 p4 a25 p3 a26 p2 a27 p1 a28 r1 a29 r3 a30 r5 a31 r4 tt0 f1 tt1 g4 tt2 g3 tt3 g2 tt4 f2 tbst d3 tsiz0 c1 tsiz1 e4 tsiz2 d2 tsiz3 f5 aack f3 artry e1 dbg v1 dbb/irq3 v2 d0 b20 d1 a18 d2 a16 d3 a13 d4 e12 d5 d9 d6 a6 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 36 freescale semiconductor pinout d7 b5 d8 a20 d9 e17 d10 b15 d11 b13 d12 a11 d13 e9 d14 b7 d15 b4 d16 d19 d17 d17 d18 d15 d19 c13 d20 b11 d21 a8 d22 a5 d23 c5 d24 c19 d25 c17 d26 c15 d27 d13 d28 c11 d29 b8 d30 a4 d31 e6 d32 e18 d33 b17 d34 a15 d35 a12 d36 d11 d37 c8 d38 e7 d39 a3 d40 d18 d41 a17 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 37 pinout d42 a14 d43 b12 d44 a10 d45 d8 d46 b6 d47 c4 d48 c18 d49 e16 d50 b14 d51 c12 d52 b10 d53 a7 d54 c6 d55 d5 d56 b18 d57 b16 d58 e14 d59 d12 d60 c10 d61 e8 d62 d6 d63 c2 dp0/rsrv /ext_br2 b22 irq1 /dp1/ext_bg2 a22 irq2 /dp2/tlbisync /ext_dbg2 e21 irq3 /dp3/ckstp_out /ext_br3 d21 irq4 /dp4/core_sreset /ext_bg3 c21 irq5 /dp5/tben /ext_dbg3 b21 irq6 /dp6/cse0 a21 irq7 /dp7/cse1 e20 psdval v3 ta c22 tea v5 gbl/irq1 w1 ci /baddr29/irq2 u2 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 38 freescale semiconductor pinout wt /baddr30/irq3 u3 l2_hit/irq4 y4 cpu_bg /baddr31/irq5 u4 cpu_dbg r2 cpu_br y3 cs0 f25 cs1 c29 cs2 e27 cs3 e28 cs4 f26 cs5 f27 cs6 f28 cs7 g25 cs8 d29 cs9 e29 cs10 /bctl1 f29 cs11 /ap0 g28 baddr27 t5 baddr28 u1 ale t2 bctl0 a27 pwe0/psddqm0/pbs0 c25 pwe1/psddqm1/pbs1 e24 pwe2/psddqm2/pbs2 d24 pwe3/psddqm3/pbs3 c24 pwe4/psddqm4/pbs4 b26 pwe5/psddqm5/pbs5 a26 pwe6/psddqm6/pbs6 b25 pwe7/psddqm7/pbs7 a25 psda10/pgpl0 e23 psdwe /pgpl1 b24 poe /psdras /pgpl2 a24 psdcas /pgpl3 b23 pgta /pupmwait/pgpl4/ppbs a23 psdamux/pgpl5 d22 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 39 pinout lwe0/lsddqm0/lbs0 /pci_cfg0 (1) h28 lwe1/lsddqm1/lbs1/pci_cfg1 1 h27 lwe2/lsddqm2/lbs2/pci_cfg2 1 h26 lwe3/lsddqm3/lbs3/pci_cfg3 1 g29 lsda10/lgpl0/pci_modckh0 1 d27 lsdwe /lgpl1/pci_modckh1 1 c28 loe /lsdras /lgpl2/pci_modckh2 1 e26 lsdcas /lgpl3/pci_modckh3 1 d25 lgta /lupmwait/lgpl4/lpbs c26 lgpl5/lsdamux/pci_modck 1 b27 lwr d28 l_a14/par 1 n27 l_a15/frame 1 /smi t29 l_a16/trdy 1 r27 l_a17/irdy 1 /ckstp_out r26 l_a18/stop 1 r29 l_a19/devsel 1 r28 l_a20/idsel 1 w29 l_a21/perr 1 p28 l_a22/serr 1 n26 l_a23/req0 1 aa27 l_a24/req1 1 /hsejsw 1 p29 l_a25/gnt0 1 aa26 l_a26/gnt1 1 /hsled 1 n25 l_a27/gnt2 1 /hsenum 1 aa25 l_a28/rst 1 /core_sreset ab29 l_a29/inta 1 ab28 l_a30/req2 1 p25 l_a31/dllout 1 ab27 lcl_d0/ad0 1 h29 lcl_d1/ad1 1 j29 lcl_d2/ad2 1 j28 lcl_d3/ad3 1 j27 lcl_d4/ad4 1 j26 lcl_d5/ad5 1 j25 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 40 freescale semiconductor pinout lcl_d6/ad6 1 k25 lcl_d7/ad7 1 l29 lcl_d8/ad8 1 l27 lcl_d9/ad9 1 l26 lcl_d10/ad10 1 l25 lcl_d11/ad11 1 m29 lcl_d12/ad12 1 m28 lcl_d13/ad13 1 m27 lcl_d14/ad14 1 m26 lcl_d15/ad15 1 n29 lcl_d16/ad16 1 t25 lcl_d17/ad17 1 u27 lcl_d18/ad18 1 u26 lcl_d19/ad19 1 u25 lcl_d20/ad20 1 v29 lcl_d21/ad21 1 v28 lcl_d22/ad22 1 v27 lcl_d23/ad23 1 v26 lcl_d24/ad24 1 w27 lcl_d25/ad25 1 w26 lcl_d26/ad26 1 w25 lcl_d27/ad27 1 y29 lcl_d28/ad28 1 y28 lcl_d29/ad29 1 y25 lcl_d30/ad30 1 aa29 lcl_d31/ad31 1 aa28 lcl_dp0/c0 1 /be0 1 l28 lcl_dp1/c1 1 /be1 1 n28 lcl_dp2/c2 1 /be2 1 t28 lcl_dp3/c3 1 /be3 1 w28 irq0/nmi_out t1 irq7/int_out/ape d1 trst ah3 tck ag5 tms aj3 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 41 pinout tdi ae6 tdo af5 tris ab4 poreset ag6 hreset ah5 sreset af6 qreq aa3 rstconf aj4 modck1/ap1/tc0/bnksel0 w2 modck2/ap2/tc1/bnksel1 w3 modck3/ap3/tc2/bnksel2 w4 xfc ab2 clkin1 ah4 pa0/restart1 /dreq3/fcc2_utm_txaddr2 ac29 (2) pa 1/ r e j ec t1 /fcc2_utm_txaddr1/done3 ac25 2 pa2/clk20/fcc2_utm_txaddr0/dack3 ae28 2 pa3/clk19/fcc2_utm_rxaddr0/dack4 /l1rxd1a2 ag29 2 pa 4/ r e j ec t2 /fcc2_utm_rxaddr1/done4 ag28 2 pa5/restart2 /dreq4/fcc2_utm_rxaddr2 ag26 2 pa6/l1rsynca1 ae24 2 pa7/smsyn2/l1tsynca1/l1gnta1 ah25 2 pa8/smrxd2/l1rxd0a1/l1rxda1 af23 2 pa9/smtxd2/l1txd0a1 ah23 2 pa10/fcc1_ut8_rxd0/fcc1_ut16_rxd8/msnum5 ae22 2 pa11/fcc1_ut8_rxd1/fcc1_ut16_rxd9/msnum4 ah22 2 pa12/fcc1_ut8_rxd2/fcc1_ut16_rxd10/msnum3 aj21 2 pa13/fcc1_ut8_rxd3/fcc1_ut16_rxd11/msnum2 ah20 2 pa14/fcc1_ut8_rxd4/fcc1_ut16_rxd12/fcc1_rxd3 ag19 2 pa15/fcc1_ut8_rxd5/fcc1_ut16_rxd13/fcc1_rxd2 af18 2 pa16/fcc1_ut8_rxd6/fcc1_ut16_rxd14/fcc1_rxd1 af17 2 pa17/fcc1_ut8_rxd7/fcc1_ut16_r xd15/fcc1_rxd0/fcc1_rxd ae16 2 pa18/fcc1_ut8_txd7/fcc1_ut16_txd15/fcc1_txd0/fcc1_txd aj16 2 pa19/fcc1_ut8_txd6/fcc1_ut16_txd14/fcc1_txd1 ag15 2 pa20/fcc1_ut8_txd5/fcc1_ut16_txd13/fcc1_txd2 aj13 2 pa21/fcc1_ut8_txd4/fcc1_ut16_txd12/fcc1_txd3 ae13 2 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 42 freescale semiconductor pinout pa22/fcc1_ut8_txd3/fcc1_ut16_txd11 af12 2 pa23/fcc1_ut8_txd2/fcc1_ut16_txd10 ag11 2 pa24/fcc1_ut8_txd1/fcc1_ut16_txd9/msnum1 ah9 2 pa25/fcc1_ut8_txd0/fcc1_ut16_txd8/msnum0 aj8 2 pa26/fcc1_utm_rxclav/fcc1_uts_rxclav/fcc1_mii_rx_er ah7 2 pa27/fcc1_ut_rxsoc/fcc1_mii_rx_dv af7 2 pa28/fcc1_utm_rxenb /fcc1_uts_rxenb /fcc1_mii_tx_en ad5 2 pa29/fcc1_ut_txsoc/fcc1_mii_tx_er af1 2 pa30/fcc1_utm_txclav/fcc1_uts_txclav/fcc1_mii_crs/ fcc1_rts ad3 2 pa31/fcc1_utm_txenb /fcc1_uts_txenb /fcc1_mii_col ab5 2 pb4/fcc3_txd3/fcc2_ut8_rxd0/l1rsynca2/fcc3_rts ad28 2 pb5/fcc3_txd2/fcc2_ut8_rxd1/l1tsynca2/l1gnta2 ad26 2 pb6/fcc3_txd1/fcc2_ut8_rxd2/l1rxda2/l1rxd0a2 ad25 2 pb7/fcc3_txd0/fcc3_txd/fcc2_ut8_rxd3/l1txda2/l1txd0a2 ae26 2 pb8/fcc2_ut8_txd3/fcc3_rxd0/fcc3_rxd/txd3/l1rsyncd1 ah27 2 pb9/fcc2_ut8_txd2/fcc3_rxd1/l1txd2a2/l1tsyncd1/l1gntd1 ag24 2 pb10/fcc2_ut8_txd1/fcc3_rxd2/l1rxdd1 ah24 2 pb11/fcc3_rxd3/fcc2_ut8_txd0/l1txdd1 aj24 2 pb12/fcc3_mii_crs/l1clkob1/l1rsyncc1/txd2 ag22 2 pb13/fcc3_mii_col/l1rqb1 /l1tsyncc1/l1gntc1/l1txd1a2 ah21 2 pb14/fcc3_mii_tx_en/rxd3/l1rxdc1 ag20 2 pb15/fcc3_mii_tx_er/rxd2/l1txdc1 af19 2 pb16/fcc3_mii_rx_er/l1clkoa1/clk18 aj18 2 pb17/fcc3_mii_rx_dv/l1rqa1/clk17 aj17 2 pb18/fcc2_ut8_rxd4/fcc2_r xd3/l1clkod2/l1rxd2a2 ae14 2 pb19/fcc2_ut8_rxd5/fcc2_rxd2/l1rqd2/l1rxd3a2 af13 2 pb20/fcc2_ut8_rxd6/fcc2_rxd1/l1rsyncd2/l1txd1a1 ag12 2 pb21/fcc2_ut8_rxd7/fcc2_rxd0/ fcc2_rxd/l1tsyncd2/l1gntd2/ l1txd2a1 ah11 2 pb22/fcc2_ut8_txd7/fcc2_txd0/ fcc2_txd/l1rxd1a1/l1rxdd2 ah16 2 pb23/fcc2_ut8_txd6/fcc2_txd1/l1rxd2a1/l1txdd2 ae15 2 pb24/fcc2_ut8_txd5/fcc2_txd2/l1rxd3a1/l1rsyncc2 aj9 2 pb25/fcc2_ut8_txd4/fcc2_txd3/l1tsyncc2/l1gntc2/l1txd3a1 ae9 2 pb26/fcc2_mii_crs/fcc2_ut8_txd1/l1rxdc2 aj7 2 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 43 pinout pb27/fcc2_mii_col/fcc2_ut8_txd0/l1txdc2 ah6 2 pb28/fcc2_mii_rx_er/fcc2_rts /l1tsyncb2/l1gntb2/txd1 ae3 2 pb29/fcc2_utm_rxclav/fcc2_uts_rxclav/l1rsyncb2/ fcc2_mii_tx_en ae2 2 pb30/fcc2_mii_rx_dv/fcc2_ut_txsoc/l1rxdb2 ac5 2 pb31/fcc2_mii_tx_er/fcc2_ut_rxsoc/l1txdb2 ac4 2 pc0/dreq1/brgo7/smsyn2 /l1clkoa2 ab26 2 pc1/dreq2/brgo6/l1rqa2 ad29 2 pc2/fcc3_cd /fcc2_ut8_txd3/done2 ae29 2 pc3/fcc3_cts /fcc2_ut8_txd2/dack2 /cts4 ae27 2 pc4/fcc2_utm_rxenb /fcc2_uts_rxenb /si2_l1st4/fcc2_cd af27 2 pc5/fcc2_utm_txclav/fcc2_uts_txclav/si2_l1st3/fcc2_cts af24 2 pc6/fcc1_cd /l1clkoc1/fcc1_utm_rxaddr2/fcc1_uts_rxaddr/ fcc1_utm_rxclav1 aj26 2 pc7/fcc1_cts /l1rqc1 /fcc1_utm_txaddr2/fcc1_uts_txaddr2/ fcc1_utm_txclav1 aj25 2 pc8/cd4 /rena4/fcc1_ut16_txd0/si2_l1st2/cts3 af22 2 pc9/cts4 /clsn4/fcc1_ut16_txd1/si2_l1st1/l1tsynca2/l1gnta2 ae21 2 pc10/cd3 /rena3/fcc1_ut16_txd2/si1_l1st4/fcc2_ut8_rxd3 af20 2 pc11/cts3 /clsn3/l1clkod1/l1txd3a2/fcc2_ut8_rxd2 ae19 2 pc12/cd2 /rena2/si1_l1st3/fcc1_utm_rxaddr1/ fcc1_uts_rxaddr1 ae18 2 pc13/cts2 /clsn2/l1rqd1 /fcc1_utm_txaddr1/ fcc1_uts_txaddr1 ah18 2 pc14/cd1 /rena1/fcc1_utm_rxaddr0/fcc1_uts_rxaddr0 ah17 2 pc15/cts1 /clsn1/smtxd2/fcc1_utm_txaddr0/ fcc1_uts_txaddr0 ag16 2 pc16/clk16/tin4 af15 2 pc17/clk15/tin3/brgo8 aj15 2 pc18/clk14/tgate2 ah14 2 pc19/clk13/brgo7/spiclk ag13 2 pc20/clk12/tgate1 ah12 2 pc21/clk11/brgo6 aj11 2 pc22/clk10/done1 ag10 2 pc23/clk9/brgo5/dack1 ae10 2 pc24/fcc2_ut8_txd3/clk8/tout4 af9 2 pc25/fcc2_ut8_txd2/clk7/brgo4 ae8 2 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 44 freescale semiconductor pinout pc26/clk6/tout3 /tmclk aj6 2 pc27/fcc3_txd/fcc3_txd0/clk5/brgo3 ag2 2 pc28/clk4/tin1/tout2 /cts2 /clsn2 af3 2 pc29/clk3/tin2/brgo2/cts1 /clsn1 af2 2 pc30/fcc2_ut8_txd3/clk2/tout1 ae1 2 pc31/clk1/brgo1 ad1 2 pd4/brgo8/l1tsyncd1/l1gntd1/fcc3_rts /smrxd2 ac28 2 pd5/fcc1_ut16_txd3/done1 ad27 2 pd6/fcc1_ut16_txd4/dack1 af29 2 pd7/smsyn1/fcc1_utm_txaddr3/fcc1_uts_txaddr3/ fcc2_utm_txaddr4/fcc1_txclav2 af28 2 pd8/smrxd1/fcc2_ut_txprty/brgo5 ag25 2 pd9/smtxd1/fcc2_ut_rxprty/brgo3 ah26 2 pd10/l1clkob2/fcc2_ut8_rxd1/l1rsyncb1/brgo4 aj27 2 pd11/l1rqb2 /fcc2_ut8_rxd0/l1tsyncb1/l1gntb1 aj23 2 pd12/si1_l1st2/l1rxdb1 ag23 2 pd13/si1_l1st1/l1txdb1 aj22 2 pd14/fcc1_ut16_rxd0/l1clkoc2/i2cscl ae20 2 pd15/fcc1_ut16_rxd1/l1rqc2 /i2csda aj20 2 pd16/fcc1_ut_txprty/l1tsyncc1/l1gntc1/spimiso ag18 2 pd17/fcc1_ut_rxprty/brgo2/spimosi ag17 2 pd18/fcc1_utm_rxaddr4/fcc1_uts_rxaddr4/ fcc1_utm_rxclav3/fcc2_utm_rxaddr3/spiclk af16 2 pd19/fcc1_utm_txaddr4/fcc1_uts_txaddr4/ fcc1_utm_txclav3/fcc2_utm_txaddr3/spisel/brgo1 ah15 2 pd20/rts4 /tena4/fcc1_ut16_rxd2/l1rsynca2 aj14 2 pd21/txd4/fcc1_ut16_rxd3/l1rxd0a2/l1rxda2 ah13 2 pd22/rxd4/fcc1_ut16_txd5/l1txd0a2/l1txda2 aj12 2 pd23/rts3 /tena3/fcc1_ut16_rxd4/l1rsyncd1 ae12 2 pd24/txd3/fcc1_ut16_rxd5/l1rxdd1 af10 2 pd25/rxd3/fcc1_ut16_txd6/l1txdd1 ag9 2 pd26/rts2 /tena2/fcc1_ut16_rxd6/l1rsyncc1 ah8 2 pd27/txd2/fcc1_ut16_rxd7/l1rxdc1 ag7 2 pd28/rxd2/fcc1_ut16_txd7/l1txdc1 ae4 2 pd29/rts1 /tena1/fcc1_utm_rxaddr3/fcc1_uts_rxaddr3/ fcc1_utm_rxclav2/fcc2_utm_rxaddr4 ag1 2 table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 45 pinout pd30/fcc2_utm_txenb /fcc2_uts_txenb /txd1 ad4 2 pd31/rxd1 ad2 2 vccsyn ab3 vccsyn1 b9 gndsyn ab1 clkin2 1,(3) ae11 spare4 (4) u5 pci_mode 1,(5) af25 spare6 4 v4 thermal0 (6) aa1 thermal1 6 ag4 i/o power ag21, ag14, ag8, aj1, aj2, ah1, ah2, ag3, af4, ae5, ac27, y27, t27, p27, k26, g27, ae25, af26, ag27, ah28, ah29, aj28, aj29, c7, c14, c16, c20, c23, e10, a28, a29, b28, b29, c27, d26, e25, h3, m4, t3, aa4, a1, a2, b1, b2, c3, d4, e5 core power u28, u29, k28, k29, a9, a19, b19, m1, m2, y1, y2, ac1, ac2, ah19, aj19, ah10, aj10, aj5 ground aa5, af21, af14, af8, ae7, af11, ae17, ae23, ac26, ab25, y26, v25, t26, r25, p26, m25, k27, h25, g26, d7, d10, d14, d16, d20, d23, c9, e11, e13, e15, e19, e22, b3, g5, h4, k5, m3, p5, t4, y5, aa2, ac3 notes: 1. mpc8265 and mpc8266 only. 2. the default configuration of the cpm pins (pa[0?31], pb[4?31], pc[0?31], pd[4?31]) is input. to prevent excessive dc current, it is recommended to either pull unused pins to gnd or vddh, or to configure them as outputs. 3. on pci devices (mpc8265 and mpc8266) this pin should be used as clkin2. on non-pci devices (mpc8260a and mpc8264) this is a spare pin that must be pulled down or left floating. 4. must be pulled down or left floating. 5. on pci devices (mpc8265 and mpc8266) this pin should be asserted if the pci function is desired or pulled up or left floating if pci is not desired. on non-pci devices (mpc8260a and mpc8264) this is a spare pin that must be pulled up or left floating. 6. for information on how to use this pin, refer to mpc8260 powerquicc ii thermal resistor guide available at www.freescale.com. table 20. pinout list (continued) pin name ball
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 46 freescale semiconductor package description symbols used in table 20 are described in table 21 . 5 package description the following sections provide the package parame ters and mechanical dimensions for the mpc826xa. 5.1 package parameters package parameters are provided in table 22 . the package type is a 37.5 x 37.5 mm, 480-lead tbga. table 21. symbol legend symbol meaning overbar signals with overbars, such as ta , are active low. utm indicates that a signal is part of the utopia master interface. uts indicates that a signal is part of the utopia slave interface. ut8 indicates that a signal is part of the 8-bit utopia interface. ut16 indicates that a signal is part of the 16-bit utopia interface. mii indicates that a signal is part of the media independent interface. table 22. package parameters parameter value package outline 37.5 x 37.5 mm interconnects 480 (29 x 29 ball array) pitch 1.27 mm nominal unmounted package height 1.55 mm
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 47 package description 5.2 mechanical dimensions figure 15 provides the mechanical dimensions and bottom surface nomenclature of the 480 tbga package. figure 15. mechanical dimensions and bottom surface nomenclature dim millimeters min max a 1.45 1.65 a1 0.60 0.70 a2 0.85 0.95 a3 0.25 ? b 0.65 0.85 d 37.50 bsc d1 35.56 ref e 1.27 bsc e 37.50 bsc e1 35 56 ref notes: 1. dimensions and tolerancing per asme y14.5m-1994. 2. dimensions in millimeters. 3. dimension b is measured at the
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 48 freescale semiconductor ordering information 6 ordering information figure 16 provides an example of the freescale part numbering nomenclature for the mpc826xa. in addition to the processor frequency, the part numberi ng scheme also consists of a part modifier that indicates any enhancement(s) in the part from th e original production design. each part number also contains a revision code that refers to the die mask revision number and is specified in the part numbering scheme for identification purposes only. for more information, contact your local freescale sales office. figure 16. freescale part number key 7 document revision history table 23 lists significant changes in each revision of this document. table 23. document revision history revision date substantive changes 0 ? initial version 0.1 8/2001 ta b l e 8 : change to sp20/sp21. 0.2 11/2001 revision of tab le 5 , ?power dissipation? modifications to figure 9 , ta ble 2 , ta b l e 1 0 , ta b l e 1 1 , and ta b l e 1 8 modification to pinout diagram, figure 13 additional revisions to text and figures throughout product code device number process technology package zu = 480 tbga processor frequency die revision level mpc 826x a (none = 0.29 micron c zu xxx (cpu/cpm/bus) x a = 0.25 micron) temperature range (blank = 0 to 105 c c = -40 to 105 c vr = 516 pbga
mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 49 document revision history 0.3 11/2001 ta b l e 1 : note 3 section 2.1: removal of ?warning? recommending use of bootstrap diodes. they are not needed. ta b l e 9 : change to sp12. ta b l e 1 0 : change to sp32. note 2 for ta ble 1 6 and table 17 addition of note at beginning of section 3.2 note 1 for ta ble 1 8 and table 19 ta b l e 2 0 : additions to b27, c28, d25, d27, e26, g29, h26?28, n25, p29, af25, aa25, ab27 0.4 2/2002 note 2 for ta b l e 2 (changes in italics): ?...greater than or equal to 266 mhz, 200 mhz cpm...? ta b l e 1 9 : core and bus frequency values for the following ranges of modck_hmodck: 0011_000 to 0011_100 and 1011_000 to 1011_1000 ta b l e 2 0 : notes added to pins at ae11, af25, u5, and v4. 0.5 3/2002 ta b l e 2 0 : modified notes to pins ae11 and af25. ta b l e 2 0 : addition of note to pins aa1 and ag4 (therm0 and therm1). 0.6 3/2002 ta b l e 2 0 : modified notes to pins ae11 and af25. 0.7 5/2002 section 1, ?features ?: minimum supported core frequency of 150 mhz section 1, ?features ?: updated performance values (under ?dual-issue integer core?) ta b l e 2 : note 2 (changes in italics): ?... less than or equal to 233 mhz, 166 mhz cpm...? ta b l e 2 : addition of note 3. 0.8 1/2003 ta b l e 2 : modification to supply voltage ranges reflected in notes 2, 3, and 4. ta b l e 4 : addition of jb and jc . ta b l e 7 , figure 8 : addition of sp42a/sp43a. figure 3 , figure 4 : addition of note for fcc output. figure 5 , figure 6 , figure 7 : addition of notes. ta b l e 1 4 , ta b l e 1 7 , and table 19 : removal of pll bypass mode from clock tables. 0.9 8/2003 note : in revision 0.3, sp30 ( ta ble 1 0 ) was changed. this change was not previously recorded in this ?document revision history? table. removal of ?hip4 powerquicc ii documentation? table. these supplemental specifications have been replaced by revision 1 of the mpc8260 powerquicc ii? family reference manual . figure 1 and section 1, ?features ?: addition of mpc8255 notes addition of figure 2 addition of vccsyn to ?note: core, pll, and i/o supply voltages? following ta b l e 2 addition of note 1 to tab le 3 ta b l e 4 : changes to ja and jb and jc . addition of notes or modifications to figure 6 , figure 7 , and figure 8 ta b l e 9 : change of sp10. addition of ta b l e 1 5 . addition of note 2 to tab le 2 0 ta b l e 2 0 : addition of fcc2 rx and tx [3,4] to cpm pins pd7, pd18, pd19, and pd29. also, the addition of spiclk to pc19. they are documented correctly in the parallel i/o ports chapter in the mpc8260 powerquicc ii? family reference manual but had previously been omitted from ta b l e 2 0 . 1.0 9/2005 document template update 1.1 0 3 /2006 addition of ta b l e 1 2 . table 23. document revision history (continued) revision date substantive changes
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mpc8260a powerquicc? ii integrated communications processor hardware specifications, rev. 1.1 freescale semiconductor 51 document revision history this page intentionally left blank
document number: mpc8260aec rev. 1.1 03/2006 freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2003 , 2006. information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. how to reach us: home page: www.freescale.com email: support@freescale.com usa/europe or locations not listed: freescale semiconductor technical information center, ch370 1300 n. alma school road chandler, arizona 85224 1-800-521-6274 480-768-2130 support@freescale.com europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) support@freescale.com japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku tokyo 153-0064, japan 0120 191014 +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate, tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor @hibbertgroup.com

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